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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/116044

    Title: An Erase Efficiency Boosting Strategy for 3D Charge Trap NAND Flash
    Authors: Shuo-Han Chen;Yuan-Hao Chang;Yu-Pei Liang;Hsin-Wen Wei;Wei-Kuan Shih
    Keywords: Multi-block erase;3D charge trap;garbage collection;3D NAND flash;flash storage
    Date: 2018-03-22
    Issue Date: 2019-03-23 12:10:34 (UTC+8)
    Publisher: IEEE
    Abstract: Owing to the fast-growing demands of larger and faster NAND flash devices, new manufacturing techniques have accelerated the down-scaling process of NAND flash memory. Among these new techniques, 3D charge trap flash is considered to be one of the most promising candidates for the next-generation NAND flash devices. However, the long erase latency of 3D charge trap flash becomes a critical issue. This issue is exacerbated because the distinct transient voltage shift phenomenon is worsened when the number of program/erase cycle increases. In contrast to existing works that aim to tackle the erase latency issue by reducing the number of block erases, we tackle this issue by utilizing the “multi-block erase” feature. In this work, an erase efficiency boosting strategy is proposed to boost the garbage collection efficiency of 3D charge trap flash via enabling multi-block erase inside flash chips. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving the erase efficiency and access performance of 3D charge trap flash. The results show that the erase latency of 3D charge trap flash memory is improved by 75.76 percent on average even when the P/E cycle reaches
    Relation: IEEE Transactions on Computers 67(9), p.1246 - 1258
    DOI: 10.1109/TC.2018.2818118
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Journal Article

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