English  |  正體中文  |  简体中文  |  Items with full text/Total items : 54566/89241 (61%)
Visitors : 10578703      Online Users : 51
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/115180


    Title: An FET With a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications
    Authors: Hsieh, Yu-Feng;Chen, Si-Hua;Chen, Nan-Yow;Lee, Wen-Jay;Tsai, Jyun-Hwei;Chen, Chun-Nan;Chiang, Meng-Hsueh;Lu, Darsen D.;Kao, Kuo-Hsing
    Keywords: Field effect transistors;Silicon;Tunneling;Heterojunctions;Logic gates;Effective mass
    Date: 2018-01-23
    Issue Date: 2018-10-11 12:10:46 (UTC+8)
    Publisher: IEEE
    Abstract: A device design technique using tunneling barriers (TBs) for reducing the short-channel effects (SCEs) is proposed. By introducing TBs at the source and drain junctions of a Si FET, the threshold voltage (Vth) rolloff can be significantly suppressed. This is because the TBs weaken the electrical coupling between drain bias and transmission/current spectrum in energy. Specifically, as compared with a conventional FET, the Vth roll-off for channel length reduction from 20 to 5 nm is mitigated by more than 40% when a thin TB is embedded at the source junction. This paper further reveals that the TB at the source junction dominates the physical mechanism minimizing the SCEs of the TBFET, and thus the device performance can be improved appreciably by removing the TB at the drain side and by decreasing the TB height at the source side.
    Relation: IEEE TRANSACTIONS ON ELECTRON DEVICES ,65(3) ,P.855-859
    DOI: 10.1109/TED.2018.2791467
    Appears in Collections:[Graduate Institute & Department of Physics] Journal Article

    Files in This Item:

    File Description SizeFormat
    An FET With a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications.pdf1375KbAdobe PDF0View/Open
    index.html0KbHTML45View/Open

    All items in 機構典藏 are protected by copyright, with all rights reserved.


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback