Enabling union page cache to boost file access performance of NVRAM-based storage device

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Proceeding > Item 987654321/114978

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Title:	Enabling union page cache to boost file access performance of NVRAM-based storage device
Authors:	Chen, Shuo-Han;Chen, Tseng-Yi;Chang, Yuan-Hao;Wei, Hsin-Wen;Shih, Wei-Kuan
Keywords:	NVRAM;page cache;mobile computing systems;FAT
Date:	2018-06-24
Issue Date:	2018-09-20 12:12:28 (UTC+8)
Abstract:	Due to the fast access performance, byte-addressability, and non-volatility of non-volatile random access memory (NVRAM), NVRAM has emerged as a popular candidate for the design of memory/storage systems on mobile computing systems. For example, the latest 3D xPoint memory could be a kind of NVRAM with much longer life expectancy than NAND ash and could ease the possible endurance issue. When NVRAM is considered as both main memory and storage in mobile computing systems, existing page cache mechanisms introduce too many unnecessary data movements between main memory and storage. To resolve this issue, we propose the concept of “union page cache,” which jointly manages data of the page cache in both main memory and storage. To realize this concept, a partial page cache strategy is designed to consider both main memory and storage as its management space and to eliminate unnecessary data movements between main memory and storage without sacricing the data consistency of le systems. Experimental results show that the proposed strategy can boost the le accessing performance upto 85.62% when using PCM as a case study.
Relation:	In the proceedings of DAC 172:1-172:6
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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