本論文『三維積體電路矽穿孔之內建自我測試與內建自我雙通道修復研究設計』，針對三維積體電路（Three-Dimensional Integrated Circuit, 3D ICs）中的矽穿孔（Through Silicon Via, TSV）規劃設計一內建自我測試與自我雙通道修復的架構。三維積體電路主要是由使用矽穿孔來作為垂直方向的通道，矽穿孔常因製程中的失誤產生錯位錯誤（Misalignment）以及隨機錯誤（Random Defect），使得矽穿孔無法正確的傳遞訊號。本論文擬針對錯誤矽穿孔設計一內建自我修復架構，針對錯誤的矽穿孔做取代修復的動作，提升整體電路之良率。 This paper "the three-dimensional integrated circuit silicon perforation built-in self test and built-in double channel self repair design" for 3D ICs (Three-Dimensional Integrated Circuit 3D ICs) Through in Silicon Via, TSV planning and design a built-in self testing and self repair of double channel architecture. Three dimensional integrated circuit mainly by using silicon holes as vertical channels, often because of perforated silicon process fault dislocation error (Misalignment) and random error (Random Defect), which can not correctly transfer signal silicon perforation. This thesis intends to design an internal self repairing architecture for the wrong silicon perforation, which will replace the repair of the wrong silicon hole, and improve the overall circuit yield.
