本文提出了一種套用在二維多階基於整數代數的Daub-4小波濾波器架構，它改善了原先的設計，除了能有的效降低濾波器對加法器的需求之外，甚至在二維運算中，節省了一個垂直方向的Daub-4濾波器架構。在這種基於整數代數的多階編碼架構中，有著無乘法器以及精準運算的優點。而為了更加改善濾波器對於硬體的需求，所以改變了資料讀取的順序，以降低轉至記憶體的大小，本文在Daub-4濾波器中，使用隔行運算的方式，能使轉至記憶體的大小從N×N縮小到10，其中N是處理中影像的長跟寬度。最後使用Xilinx Zedboard測試開發版，實現經過改良的一階跟多階二維Daub-4超大積體電路架構，並使用各種不同的圖像進行測試。 This paper proposes a novel architecture for algebraic integer (AI) based multi encoding of 2-D Daubechies-4 wavelet filters. This architecture improves on previous designs, which can significantly reduce the requirement of the adders. Moreover, it also reduces one of 1-D Daubechies-4 wavelet filters in algebraic integer (AI) block. The multi encoded AI framework allows a multiplication-free and computationally accurate architecture. In order to reduce the transpose memory (TM), the 2-D Daubechies-4 wavelet filters will operates follow by Interlaced Read Scan Algorithm (IRSA). The size of the transpose memory (TM) block can be reduced from N×N to 2N as well as increase speed to calculate final value output. The 2-D Daubechies-4 single and multi-level VLSI architectures are implemented on a Xilinx Virtex-6 xc7z020-1clg484 field programmable gate array (FPGA) device. The designs were tested with different gray image size of 512×512 .
