A Fast-Lock and Low-Power DLL-Based Clock Generator Applied for DDR4

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Journal Article > Item 987654321/112391

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Title:	A Fast-Lock and Low-Power DLL-Based Clock Generator Applied for DDR4
Authors:	Yu-Lung Lo;Wei-Bin Yang;Han-Hsien Wang;Cing-Huan Chen;Zi-Ang Huang
Date:	2018-01
Issue Date:	2017-12-13 02:10:37 (UTC+8)
Abstract:	This paper presents a fast-lock and low-power delay-locked loop (DLL) circuit applied for DDR4. The proposed modified phase detector and modified charge pump can reduce locking time as well as static phase error. The glitch elimination circuit reduces glitches in the PD for reducing the glitch power. The phase interpolator and phase combiner circuit are used to generate four output frequencies: 0.2, 0.4, 0.8, and 1.6 GHz. The design is fabricated through a 0.18-μm standard CMOS process with a supply voltage of 1.8 V. The simulation results indicate that the lock time is less than 20 cycles and the power consumption of the DLL is 15.14 mW at 1.6 GHz. The active die area of the proposed DLL-based clock generator is 0.51 mm2.
Relation:	Microsystem Technologies 24(1), p.137–146
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

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