All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Journal Article > Item 987654321/112389

Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/112389

Title:	All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application
Authors:	Chih-Wei Tsai;Yu-Lung Lo;Chia-Chen Chang;Han-Ying Liu;Wei-Bin Yang;Kuo-Hsing Cheng
Date:	2017-01-30
Issue Date:	2017-12-13 02:10:33 (UTC+8)
Abstract:	A synchronous and highly accurate all-digital duty-cycle corrector (ADDCC), which uses simplified dual-loop architecture, is presented in this paper. To explain the operational principle, a detailed circuit description and formula derivation are provided. To verify the proposed design, a chip was fabricated through the 0.18-µm standard complementary metal oxide semiconductor process with a core area of 0.091 mm2. The measurement results indicate that the proposed ADDCC can operate between 300 and 600 MHz with an input duty-cycle range of 40–60%, and that the output duty-cycle error is less than 1% with a root-mean-square jitter of 3.86 ps.
Relation:	Japanese Journal of Applied Physics 56(4S), p.04CF02
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

Files in This Item:

File	Size	Format
index.html	0Kb	HTML	11	View/Open