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    題名: All-digital duty-cycle corrector with synchronous and high accuracy output for double date rate synchronous dynamic random-access memory application
    作者: Chih-Wei Tsai;Yu-Lung Lo;Chia-Chen Chang;Han-Ying Liu;Wei-Bin Yang;Kuo-Hsing Cheng
    日期: 2017-01-30
    上傳時間: 2017-12-13 02:10:33 (UTC+8)
    摘要: A synchronous and highly accurate all-digital duty-cycle corrector (ADDCC), which uses simplified dual-loop architecture, is presented in this paper. To explain the operational principle, a detailed circuit description and formula derivation are provided. To verify the proposed design, a chip was fabricated through the 0.18-µm standard complementary metal oxide semiconductor process with a core area of 0.091 mm2. The measurement results indicate that the proposed ADDCC can operate between 300 and 600 MHz with an input duty-cycle range of 40–60%, and that the output duty-cycle error is less than 1% with a root-mean-square jitter of 3.86 ps.
    關聯: Japanese Journal of Applied Physics 56(4S), p.04CF02
    顯示於類別:[電機工程學系暨研究所] 期刊論文

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