淡江大學機構典藏:Item 987654321/109832
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    Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/109832


    Title: Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic
    Authors: Chen, Shuo Han;Chen, Yen-Ting;Wei, Hsin-Wen;Shih, Wei-Kuan
    Date: 2017-06-18
    Issue Date: 2017-03-09 02:10:48 (UTC+8)
    Relation: The proceedings of DAC 2017
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

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