Efficient Warranty-Aware Wear Leveling for Embedded Systems with PCM Main Memory

doi:10.1109/TVLSI.2015.2511147

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Journal Article > Item 987654321/108847

Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/108847

Title:	Efficient Warranty-Aware Wear Leveling for Embedded Systems with PCM Main Memory
Authors:	Sheng-Wei Cheng;Yuan-Hao Chang;Tseng-Yi Chen;Yu-Fen Chang;Hsin-Wen Wei;Wei-Kuan Shih
Keywords:	wear leveling;Embedded systems;operation efficiency;PCM main memory;product warranty period
Date:	2016-07-01
Issue Date:	2016-12-17 02:10:21 (UTC+8)
Publisher:	IEEE
Abstract:	Recently, phase change memory (PCM) has become a promising candidate to replace dynamic RAM as main memory due to its low power consumption, fast I/O performance, and byte addressability. Accompanied with the merits, the adoption of PCM may suffer from its physical characteristic of limited write endurance. Wear leveling is a well-known approach to address this issue. For PCM main memory, the design of wear leveling should stress operation efficiency and overhead reduction. Nevertheless, conventional designs are usually dedicated to prolonging the lifetime of PCM in the best effort. In this paper, we propose a novel perspective that, instead of valuing PCM lifetime exploitation as the first priority, we turn to satisfy the product warranty period. With such a paradigm shift, the management overhead of wear-leveling mechanisms could be reduced so as to achieve further enhancement of operation efficiency. To this end, we propose a warranty-aware page management design that introduces novel criteria used to determine the state of a page by taking both the product warranty period and the write cycles of a page into consideration. Theoretical analysis is also conducted to investigate the properties and performance of the proposed management. To show the effectiveness of the proposed design, we collected real traces by running SPEC2006 benchmarks with different write intensity workloads. The experimental results showed that our design reduced the overhead to one-third that of the state-of-the-art designs while still providing the same level of performance.
Relation:	IEEE Transactions on VLSI 24(7), p.2535-2547
DOI:	10.1109/TVLSI.2015.2511147
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

Files in This Item:

File	Size	Format
Efficient Warranty-Aware Wear Leveling for Embedded Systems with PCM Main Memory.pdf	3320Kb	Adobe PDF	1	View/Open
index.html	0Kb	HTML	253	View/Open
index.html	0Kb	HTML	164	View/Open

Loading...