English  |  正體中文  |  简体中文  |  Items with full text/Total items : 49983/85139 (59%)
Visitors : 7804467      Online Users : 118
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/107373


    Title: Hardware accelerator design for image processing
    Authors: Li, S.A.;Wong, C.C.;Yang, C.Y.;Chen, L.F.
    Keywords: FPGA;human-machine interface;hardware accelerator
    Date: 2012-08-20
    Issue Date: 2016-08-18 13:39:12 (UTC+8)
    Publisher: Berlin: Springer Berlin Heidelberg
    Abstract: This paper proposed an image processing system based on hardware accelerator design method in FPGA chip. The architectures of the image system will be described. A hardware accelerator for scaling image is designed with Avalon-MM burst mode in System-on-a-Programmable-Chip (SOPC). There is a human-machine interface which display on the LCD Touch Panel Module (LTM) is designed in the image processing system. A user can choose a scaling factor by touching screen panel, and then LTM will display a 640 × 480 image on the LTM screen. Finally, the experimental result shows the comparison of the two design methods, and the hardware accelerator has better performance than Nios II processor.
    Relation: Lecture Notes in Computer Science 7429, pp.436-437
    DOI: 10.1007/978-3-642-32527-4
    Appears in Collections:[電機工程學系暨研究所] 會議論文

    Files in This Item:

    File Description SizeFormat
    index.html0KbHTML20View/Open

    All items in 機構典藏 are protected by copyright, with all rights reserved.


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback