Analysis and Design Considerations of Static CMOS Logics under Process, Voltage and Temperature Variation in UMC 0.18um CMOS Process

doi:10.1109/ISPACS.2015.7432737

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題名:	Analysis and Design Considerations of Static CMOS Logics under Process, Voltage and Temperature Variation in UMC 0.18um CMOS Process
作者:	Yang, Wei-Bin;Lin, Yu-Yao;Wang, Chi-Hsiung;Chang, Kuo-Ning;Chen, Cing-Huan;Lo, Yu-Lung
關鍵詞:	UMC 0.18um CMOS process;size ratio;ProcessVoltage-Temperature (PVT) variations;threshold voltage;ultralow voltage
日期:	2015-11-09
上傳時間:	2016-08-18 13:38:45 (UTC+8)
出版者:	IEEE
摘要:	In this paper, we analyze the circuit characteristic of static CMOS logics and provide the size ratio of PMOS to NMOS transistors under process, voltage and temperature (PVT) variations in UMC 0.18 μm CMOS process. The threshold voltage of a MOS transistor is influenced seriously under PVT variations with different channel length setting. The performances of the static CMOS logics are unstable in ultralow voltage. To find the best size ratio of PMOS to NMOS transistors, NOT gate are simulated with various channel length setting and PVT conditions. Five stages of NOT gate are designed by different ratios respectively to compose the ring oscillator. By examining oscillator output frequency, then we analyze the change of current according to various channel length and PVT conditions. By further analyzing the simulation results, if the channel length of MOS transistors is shorter than 300nm, or the supply voltage is lower than 0.9 V, then the performance of MOS transistors is unstable in UMC 0.18 μm CMOS process. Through the data and the simulation provided by this paper, we can design the circuits with different needs, and we can also understand how each different section of PVT variations and channel length setting will affect the circuit in UMC 0.18 μm CMOS process.
關聯:	ISPACS proceeding , pp.57-61
DOI:	10.1109/ISPACS.2015.7432737
顯示於類別:	[電機工程學系暨研究所] 會議論文

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