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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/106673

    Title: 重分佈層之避障繞線演算法
    Other Titles: Obstacle-Avoiding Routing Algorithm for Redistribution Layer
    Authors: 饒建奇;王偉丞
    Keywords: 繞線;重分佈層;覆晶技術;避障;routing;RDL;flip-chip;obstacle-avoiding
    Date: 2015-11-28
    Issue Date: 2016-04-27 11:20:38 (UTC+8)
    Abstract: 重分佈層(RDL,Redistribution Layer)目前多使用在覆晶技術(Flip-Chip)上,而覆晶技術是一種將IC與基板(substrate)相互連接,基於小尺寸晶片、高I/O密度的封裝(Packging)方法。在封裝的過程中,先將晶片的墊片(pad)長出凸塊(bump),然後將其翻覆過來,以面朝下的方式讓晶片上的墊片透過金屬導體與基板的接合點相互連接的封裝技術。
    然而,覆晶技術最初的I/O接點並不具有面陣列(area array)的設計,使得此技術在早期受到不小的阻礙,於是才出現了重分佈層這樣的技術來解決這個問題,重分佈層是在晶圓表面沉積金屬層和介質層並形成相應的金屬佈線,來對晶片的I/O接點進行重新佈局,將其以面陣列形式佈置到較寬鬆的區域。
    繞線演算法之目的為,讓晶片四個邊緣的I/O接腳(I/O pad)重新分布到平面陣列的凸塊墊片(bump pad)上。
    RDL, redistribution layer, mostly applies on Flip-Chip technology in recent years. Here is the mention of Flip-Chip technology, which connecting both integrated circuit and the substate together, based on small-size chip and high-IO-density packaging. In the package process, first, deposits solder balls on each of the pads. And then, flipped and positioned, so that the solder balls will facing the connectors on the external circuitry.
    However, in the early, Flip-Chip's I/O ports doesn't have plane array designing. So it receives a big difficulty when developing. To solve this problem, the designing of redistribution layer is came out. Redistribution layer is a re-routing layer between deposited metal layer and medium layer. It redistributes I/O port into plane array at wider area.
    Though, Flip-Chip technology is getting more mature nowadays, the amount of related papers are also getting much more. And this paper is focused on when the obstacles exist in the redistribution layer and affect the routing process, how we plan the new routing against it. There has a previous work "Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs." Then we refer their model and improve it with simpler method to reduce its complexity.
    The purpose of the routing algorithm is to redistribute the route from the I/O pads which aroundding the origin chip to the bump pads which scattering in the plan area.
    The method of previous work is divided into two parts: Global Routing and Detail Routing.
    Then, Global Routing is divided into four steps: 1) tile partition, 2) tile merging, 3) flow-network, and 4) minimum-cost-flow solving.
    Step one, the routing plane is partitioned into a number of local regions called "tiles". Step two, merge some tiles based on a dynamic programming algorithm to improve solution quality and reduce the problem size. Step three, connect all models together, producing a global flow network. Step four, apply the minimum-cost maximum-flow algorithm to the network. Finally, transform the network-flow result into global routing topology. Then, based on the routing topology, detailed routing determines the specific wiring locations and completes the routing procedure.
    Comparing to the previous work, our method omitted the second part. Because this step restrict that the edge of each tile can only have one opening at most, which means that the edge cannot have more than two obstacle aside. In consequence, this step cannot guaranteed that the result will be better. So, if we omit this step, not also reduce the complexity of algorithm, but also avoid the case that even worse.
    Relation: 2015年民生電子研討會 WCE2015
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

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