English  |  正體中文  |  简体中文  |  Items with full text/Total items : 49983/85139 (59%)
Visitors : 7802479      Online Users : 102
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/106172


    Title: Low-cost and high-speed hardware implementation of contrast-preserving image dynamic range compression for full-HD video enhancement
    Authors: Shih-An Li;Chi-Yi Tsai
    Keywords: approximation theory;data compression;field programmable gate arrays;image colour analysis;image enhancement;video coding
    Date: 2015/07/27
    Issue Date: 2016-04-22 13:22:57 (UTC+8)
    Publisher: The Institution of Engineering and Technology
    Abstract: This study presents a cost-efficient and high-performance field programmable gate array (FPGA)-based hardware implementation of a contrast-preserving image dynamic range compression algorithm, which is an important function used in modern digital video cameras and displays to improve visual quality of standard dynamic range colour images (8 bits/channel). To achieve this purpose, a hardware-friendly approximation to an existing fast dynamic range compression with local contrast preservation (FDRCLCP) algorithm is proposed. The computation of the proposed approximated FDRCLCP algorithm requires only fixed-point unsigned binary addition, multiplication, and bit-shifting. Moreover, the proposed hardware implementation uses a line buffer instead of a frame buffer to process whole image data. These advantages significantly improve throughput performance and reduce memory requirement of the system. The FPGA implementation of the proposed algorithm requires only about 98 K bits on-chip memory and achieves about 170.24 MHz operating frequency by using an Altera Cyclone II device. This is a large improvement compared with the existing results as it is quick enough to process full high-definition videos (1920 × 1080 pixels) at least 80 frames per second using a low-cost FPGA device.
    Relation: IET Image Processing 9(8), pp.605-614
    DOI: 10.1049/iet-ipr.2014.0162
    Appears in Collections:[電機工程學系暨研究所] 期刊論文

    Files in This Item:

    File Description SizeFormat
    index.html0KbHTML44View/Open

    All items in 機構典藏 are protected by copyright, with all rights reserved.


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback