權重H2降階控制器設計及硬體迴路模擬

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Title:	權重H2降階控制器設計及硬體迴路模擬
Other Titles:	Design and hard ware-in-the-loop simulation of weighted H2 reduced-order controllers
Authors:	吳達太;Wu, Da-Tai
Contributors:	淡江大學電機工程學系碩士班周永山;李世安;Chou, Yung-Shan;Li, Shih‐An
Keywords:	權重函數;H2控制;降階;區域極點配置;FPGA;硬體迴路模擬;weighting functions;loop shaping;control;Reduced-Order;regional pole placement;Hardware-in-the-loop
Date:	2015
Issue Date:	2016-01-22 15:06:54 (UTC+8)
Abstract:	本文研究權重降階控制器設計之問題。傳統方法引入權重函數會造成控制器階數增加，並且在擴增系統內產生一些無法移動的極點，造成閉迴路極點配置的困難。本文針對這兩點提出改善的方法，利用僅併入權重函數的一部分而非全部，配合特殊之變數設定，推導出權重性能之充分條件。如此，可彈性調整控制器階數使其介於受控體階數以及受控體與權重函數階數總和之間。另外，本文所提的方法，不管權重函數的極點是否落在指定的極點配置區域中，仍能進行區域極點配置。本論文所提出的設計條件皆為線性矩陣不等式(Linear Matrix Inequalities，LMIs)，可利用MATLAB軟體求解以及數值模擬驗證。最後，本文在FPGA(DE2-115)開發板上，運用硬體描述語言將所設計出之控制器實現在硬體上。再與Simulink作結合，透過硬體迴路模擬證實我們所提方法之可行性。 This thesis investigates the problem of weighted reduced-order controller design. Traditional method introduces weighting functions into the design procedure, which increases the order of the controllers. Furthermore, it leads to the situation that some poles of the augmented plant (i.e., the weighted plant) are fixed, causing difficulty in closed-loop pole placement. To make improvements concerning the two questions, only a part but not all of the weighting function is incorporated into the plant. Sufficient conditions for the problem are derived utilizing a particular choice of variables. As a result, in the affirmative case the order of the controller is equal to the sum of the plant''s order and the order of the part of the weighting function incorporated into the plant, which in total lies between the plant''s order and that of the weighted plant. In addition, the proposed method is capable of performing regional pole placement, regardless of the poles of the weighting function falling within the specified region in the complex plane or not. The solvability conditions derived for the problem are in terms of linear Matrix Inequalities (LMIs), which can be solved efficiently using MATLAB. Finally, the controller is implemented on FPGA(DE2-115) development board. When integrated with Simulink the results of the hardware-in-the-loop simulation validate the effectiveness of the proposed method.
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Thesis

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