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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/105843


    Title: 超低電壓快鎖式數位控制低壓降線性穩壓器設計
    Other Titles: Design of fast-locked digitally controlled low-dropout regulator in ultra-low voltage input
    Authors: 林鈺堯;Lin, Yu-Yao
    Contributors: 淡江大學電機工程學系碩士班
    楊維斌;Yang, Wei-Bin
    Keywords: 快速暫態響應;高電流效率;快鎖式數位控制低壓降線性穩壓器;快速追鎖機制;Fast Load Transient Response;High Current Efficiency;FDLDO;Fast-Locked Control Mechanism
    Date: 2015
    Issue Date: 2016-01-22 15:06:40 (UTC+8)
    Abstract: 隨著製程進步與消費型電子裝置的蓬勃發展,具有高續航力的規格是電子裝置一直以來都被重視的設計考量,為了提升電子裝置之續航力,除了增加電池或能源之可靠度外,在設計電路時下修操作電壓之需求來減少電路內部所消耗之功率為最直接的管道,因此,系統單晶片內之操作電壓不斷下降是時代進步的一大趨勢。近年內,高效能之電源管理系統在系統單晶片內也漸漸成為不可或缺的角色,藉由高效能之電源管理系統,針對全系統之操作狀態來控管系統單晶片之操作速度與功率消耗,在各種不同的狀態下使全系統電路得以發揮最佳化的表現。本篇論文將根據電源管理系統首要強調之快速反應時間與高電流效率為設計考量,於90奈米 CMOS製程下採用數位式控制的方式設計一超低電壓快鎖式數位控制低壓降線性穩壓器,完成適用於超低電壓系統單晶片內之高穩定性數位電路電壓源。在超低供應電壓以及較為前瞻之規格設定下,應用於超低電壓操作之電路設計成為本論文之重要議題,因此本論文將針對90奈米 CMOS製程下的MOS元件與靜態邏輯電路之各種特性參數與設計方式進行分析,並提出最佳設計考量。
    本篇論文之電路設計結合了數位控制變頻振盪電路、數位誤差偵測電路、數位邏輯控制單元、以及PMOS電源電晶體陣列四大區塊,並且運用快速鎖定機制降低系統於追鎖模式與穩壓模式時所需之暫態響應時間以及靜態電流。其中,數位控制變頻振盪電路提供全系統於追鎖模式與穩壓模式時所需之系統最佳化時脈。利用電壓控制延遲線電路與相位偵測器所組成之數位誤差偵測電路決定了穩壓器輸出電壓之可靠度及精準度。數位邏輯控制單元則由多種數位邏輯電路與十二位元上下數計數器構成,負責將數位誤差偵測電路輸出之偵測結果運算成模式判斷控制訊號與高解析度之PMOS電源電晶體陣列數位控制訊號,控制PMOS電源電晶體陣列使輸出電壓達到穩定0.3V之正負1%誤差內的預期規格,並且達到輸出電流之輕重載設計要求。本電路所使用的快速鎖定機制乃是透過穩壓器操作模式之判斷結果,使數位控制變頻振盪電路得以針對穩壓器當下之操作模式輸出最佳化系統效率之內部時脈訊號(頻寬範圍約0.7MHz至25MHz),提供給全系統之電路使用,另外,不需由外部輸入系統運作時脈的設計方式讓此穩壓器之使用者免於煩惱外部輸入時脈頻率設定的問題,使穩壓器能夠針對各種操作模式發揮最佳的效率。
    當全系統模擬於TT、FF、SS三種製程偏異與0°C、27°C、75°C三種溫度偏異下,輸出電壓皆符合預期之規格,而本論文之設計規格如下,系統之輸入電壓及操作電壓為0.35V,輸出電壓為0.3V(誤差小於±1%),最大負載電流為2.4mA,與精準度有關的負載調節率於TT製程下小於1.4mV/mA,操作溫度於0°C時最為精準,可達到0.138mV/mA,線性調節率於重載時可達到4.286mV/V,另外,在各種操作環境下,輸出電壓於追鎖狀態時的暫態響應時間皆小於200μs,且系統內部不需任何補償電容、電阻或電感等類比電路元件,全系統之電流效率高達99.8%以上。總結上述,本設計適用於整合在超低電壓系統單晶片內之高穩定性數位電路電壓源。
    With the advance of process and the growth in demand of automobile electronic devices, portable electronic devices, and wearable electronic devices, supply voltage of System-on-a-Chip (SoC) significantly decreased. The purpose of this paper is according to the most important consideration of power management system design, fast load transient response and high current efficiency, to design a fast-locked digitally controlled low-dropout regulator (FDLDO) in ultra-low voltage input and 90nm CMOS process.
    The traditional LDO is difficult to design and develop under ultra-low supply voltage due to impact of voltage headroom. On the contrary, the digitally controlled LDO could be easier operated at ultra-low supply voltage. In 90nm CMOS process, standard input voltage is 1V, even the input voltage decrease to 0.35V, the output voltage can still be 0.3V in this design. Therefore, circuits which can be operated in ultra-low voltage has become an important topic of this paper. In order to facilitate designing circuits in ultra-low voltage input, there is Monte Carlo analysis of the parameter characteristics and design consideration in 90nm CMOS process at the third chapter of this paper.
    The proposed FDLDO is composed of digitally controlled oscillator, digital error detector, digital logic control unit, and power PMOS array. By integrated four parts, and utilizing fast-locked control mechanism to reduce the settling time of load transient response and the quiescent current, the proposed FDLDO is suitable for ultra-low voltage System-on-a-Chip applications. The output voltage feedback to voltage controlled delay line for error detection with reference voltage, then, two phases with different delay time will input to phase detector for generating initial control signals. After pulse amplifier and digital logic control unit, mode selection signal and the counter control signals will be generated. Mode selection signal input to the digitally controlled oscillator for producing the optimal clock signal (700KHz–20MHz) to digital error detector and digital logic control unit. The counter control signals make the 12-bits up/down counter generate power PMOS array control signals with high resolution, to control the output voltage increase or decrease.
    This design can be operated at TT, FF, and SS regions and different temperature situation of 0°C, 27°C, and 75°C through simulations. The input voltage is set at 0.35V, and the output voltage is set at 0.3V with error less than ±1% of 0.3V. The maximum load current is 2.4mA, load regulation is less than 1.4mV/mA, line regulation is 4.286mV/V at 2.4mA, 14.285mV/V at 240uA, and current efficiency is 99.8%.
    Appears in Collections:[電機工程學系暨研究所] 學位論文

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