基於嵌入式開發板之車牌辨識系統設計與實作

機構典藏 > College of Engineering > Graduate Institute & Department of Computer Science and Information Engineering > Thesis > Item 987654321/105731

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Title:	基於嵌入式開發板之車牌辨識系統設計與實作
Other Titles:	Design and implementation of a vehicle license plate recognition system based on embedded system
Authors:	杜柏賢;Tu, Po-Hsien
Contributors:	淡江大學資訊工程學系碩士班黃連進
Keywords:	車牌辨識;車牌定位;邊緣偵測;形態學;連通物件標記;License Plate Recognition;FPGA;License Plate Positioning;Edge detection;Morphology;Connected-Component Labeling
Date:	2015
Issue Date:	2016-01-22 15:03:49 (UTC+8)
Abstract:	近年來，隨著科技進步，電腦設備無論是在計算能力還是成本上，逐漸突破以往種種限制，進而發展出許多新應用。例如國道電子收費系統以及停車場自動收費系統，透過資訊科技降低人工成本，提升服務品質。然而儘管許多科技已發展相當成熟，但生活中許多工作仍仰賴人力來進行。像是近年來，許多分工細膩、手法專業的車輛竊盜犯罪案件不斷增加。面對這樣的趨勢，如何能有效的利用科技以及有限的警力來增加執法效力便成為當今一大重要研究議題。過去已有許多實作在個人電腦或是嵌入式開發板的車牌辨識系統研究。然而，使用個人電腦雖有極佳的效能，但成本與耗能相對較高；而使用嵌入式開發板雖然耗能較低，有時卻會受限於硬體效能而無法充分發揮。因此，本論文提出利用搭載FPGA可程式化邏輯陣列的ARM嵌入式平台所實作出高辨識率的即時車牌辨識系統。希望能在低成本、低功耗與運算效能間三者之間取得平衡點。進而提高執法人員使用意願。相較於純ARM嵌入式系統，結合FPGA可程式化邏輯陣列的ARM嵌入式系統不但能保有低成本、低功耗的優點。在依照硬體特性不同，透過FPGA可程式化邏輯陣列與ARM處理器協同運算，可以避免到一些運算瓶頸，提升整體系統處理效能。由實驗結果分析，本篇論文提出車牌辨識系統能透過硬體特性，有效地降低演算法複雜度。而與一般中階個人電腦進行比較之後，部分運算效能甚至能超越中階個人電腦。而在一般使用環境，仍保有了高辨識率的優點，可以算是兼顧實用與硬體成本的車牌辨識系統。 In recent years, with advances of technology, computer equipment, both in computing power or cost, has gradually broken through numerous limitations to bring about many new applications. For instance, national highway electronic toll collection systems and parking automatic toll collection systems, thanks to information technology, have reduced labor costs and improved quality of service. Nonetheless, despite availability of mature technology, we still rely on human labor in many aspects of life which falls short of curbing the rising trend of highly specialized professional vehicle theft. Given the trend, how to effectively exploit technology and the limited police force to increase the effectiveness of law enforcement is one of the imperative research topics. In the past, there have been many implementations on PC or researches on license plate recognition embedded system development board. However, the use of personal computers, albeit with an excellent performance, are financially and energetically at high costs whereas the use of conventional embedded board, despite lower energy consumption, is at times constrained by the efficiency of the hardware to yield satisfactory results. Therefore, this thesis proposes employing the SoC FPGA embedded platforms to fabricate high performance real time license plate recognition system. We attempt at striking a balance amidst low cost, low power consumption and computing performance that may induce law enforcement officers to accept it. Compared to pure ARM embedded system, the ARM embedded system compounded with FPGA programmable logic array not only retains the advantages of low cost and low power consumption, but the collaborative computing of FPGA programmable logic array and ARM processor in accordance with the characteristics of different hardware avoids some calculations bottlenecks and improves overall system processing performance. The implementation shows that the license plate recognition system proposed in this thesis effectively makes use of the characteristics of the hardware to reduce the computation complexity. Additionally, some computations of this paper even produce better results relative to the general mid-level PC. Last but not the least, it attains high recognition performance in the general environment on implementation, proving itself a viable license plate recognition system economically and functionally.
Appears in Collections:	[Graduate Institute & Department of Computer Science and Information Engineering] Thesis

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