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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/103693

    Title: 權重H2降階控制器設計及硬體迴路模擬
    Authors: 周永山;吳達太;李世安
    Keywords: 權重函數,H2控制,降階,集點配置,FPGA,硬體迴路模型
    Date: 2015-07-02
    Issue Date: 2015-09-17 11:24:22 (UTC+8)
    Abstract: 本文研究權重H2控制器設計之問題。傳統方法會造成高階控制器(受控體與權重函數之階數總和),以及會在擴增系統內引入一些無法移動之極點,對閉迴路極點配置構成限制。本文提出改良的方法,若某些條件滿足,則可得到H2降階控制器,並且將閉迴路系統極點配置在指定區域,不受引入權重函數階數及極點位置之影響。文末利用軟體模擬暨硬體迴路模擬驗證本文方法之可行性
    Appears in Collections:[電機工程學系暨研究所] 會議論文

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