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    题名: 應用於音頻系統高解析度低功耗三角積分類比數位轉換器之研究(I)
    其它题名: The Research of High Resolution Low Power Sigma Delta Adc for Audio Applications
    作者: 江正雄
    贡献者: 淡江大學電機工程學系
    关键词: 類比數位轉換器;三角積分調變器;多位元量化器;高解析度;低功率;音頻系統;逐漸趨近式類比數位轉換器;Analog-to-digital converter (ADC);2A modulator;multi-bit quantizer;high resolution;low power;audio system;successive approximation ADC (SAR ADC)
    日期: 2012-08
    上传时间: 2015-05-20 10:07:16 (UTC+8)
    摘要: 本計畫的主要目標是研製應用於音頻系統的高解析度類比數位轉換器 (Analog-to-Digital Converter, ADC),此高解析度的ADC可應用於高品質的影音系統。 隨著可攜式裝置如智慧型手機、平板電腦、筆記型電腦、數位隨身聽等的興起,產業 界對ADC的要求除了高解析度的特性外,也著重於低功耗及低成本的考量。因此,本 計畫目標是希望實現一個24-bit EA ADC,此ADC的核心為一個多位元量化器單迴路 的三角積分調變器(EA modulator, SDM),其量化器架構係由逐漸趨近式類比數位轉換 器(Successive Approximation ADC, SAR ADC)所構成,以此降低功率消耗;此三角積分 調變器同時具有校正和補償的機制,來增加系統穩定度與高解析度。此外我們也將研 究透過系統數學模型推導進而將系統簡化,使電路設計者能很容易的就能設計製作高 解析度ADC並降低成本,最後我們會進行晶片實現、驗證、與測試。 此計畫為一個兩年期之研究計畫,預期工作項目如下所示。 第一年: (1)將SAR ADC的非理想效應數學模型化。 (2)以Matlab模擬實現24-bit低功率多位元單迴路三角積分調變器的系統架構。 (3)以Matlab實現所考量的校正與補償機制之數學模型。 (4)實現24-bit低功率多位元單迴路三角積分調變器之電路設計。 (5)晶片布局與下線量測,驗證其Matlab的數學模型。 (6)完成數學模型驗證與晶片量測,發表研究論文。 第二年: (1)實現數位降頻濾波器於FPGA/CPLD上。 (2)透過數學推導類比式校正與補償機制轉移成數位降頻濾波器的校正與補償機 制。 (3)透過Matlab實現包含校正與補償機制之數位降頻濾波器的演算法。 (4)實現24-bit低功率EA ADC之電路設計。 (5)晶片布局與下線量測,實現其包含校正與補償機制之數位降頻濾波器於 FPGA/CPLD。 (6)完成晶片與包含校正與補償機制之數位降頻濾波器的共同量測,並發表研究論 文。
    This proposal proposes to research and design an audio band high resolution analog-to-digital converter (ADC). The proposed high resolution ADC can be applied to the applications of high quality audio systems. The handheld devices, such as smart phones, tablet computers, notebook computers, and MP3 players, are very popular in recent years. For ADC specification requirements besides the high resolution characteristics, people consider the requirements of low power consumption and low cost as well. Therefore the proposed proposal tries to design and implement a 24-bit low power ADC. The core of this proposed ADC is a 3rd order single loop modulator with multi-bit quantizer. The multi-bit quantizer will be implemented by the successive approximation ADC (SAR ADC) for low power consideration. In order to keep stabilization and high resolution, the modulator will have the mechanisms of calibration and compensation. In this project we will try to simplify the architecture of the modulator by studying the mathematical model. Hopefully we can find some systematical approach to design and implement high resolution modulators easily in the future. We will further design, implement, and measure the proposed 24-bit ADC. This is a two-year research proposal, and we expect to finish the following tasks year by year. In the first year: (1) Model the non-ideality parameters of the SAR ADC. (2) Implement and simulate the architecture of the 24-bit low power modulator by Matlab. (3) Simulate the mathematical models of the mechanisms of calibration and compensation by Matlab. (4) Design the 24-bit low power modulator in the circuit level. (5) Implement and measure the modulator chip, and further verify the mathematic model. (6) Finish the chip implementation, verify the mathematical model, and publish papers. In the second year: (1) Implement the decimation filters to FPGA/CPLD. (2) Derive the mathematical theory and try to move the calibration and compensation mechanisms from the analog part to the decimation filter part. (3) Implement the calibration and compensation mechanisms in the decimation part by Matlab. (4) Implement the 24-bit low power ADC. (5) Implement and measure the chip, and implement the calibration and compensation mechanisms to FPGA/CPLD. (6) Finish the project and publish papers.
    显示于类别:[電機工程學系暨研究所] 研究報告

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