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    題名: Efficiency of arithmetic representations using hybrid number system to implement on FPGA
    其他題名: 使用混合數字系統之FPGA算術表現效能探討
    作者: 黃凱弘;Huang, Kai-Hung
    貢獻者: 淡江大學電機工程學系碩士班
    劉寅春;Liu, Peter
    關鍵詞: 混合數字系統;現場可程式邏輯閘陣列;T-S 模糊小腦模型控制器;硬體實現;Hybrid number system;Field Programmable Gate Array (FPGA);TS-CMAC;Hardware implementation
    日期: 2014
    上傳時間: 2015-05-04 10:02:20 (UTC+8)
    摘要: 本論文旨在探討將智慧型控制器透過混合數字系統之硬體架構實現於FPGA平台,並探討算術表示對於控制器計算效能的影響,同時套用TS-CMAC控制器模擬與實現;目的是透過Altera SOPC與NIOS II處理器的使用者指令集實現32位元混合數字系統處理器,並應用於TS-CMAC作為算術運算。其中,控制器的計算性能優劣取決於算術表示;然而,控制器實作上必須考量到所需要花費的FPGA邏輯元件成本,以及數字精度的影響,以上因素均會影響控整器整體效能之呈現;因此,本論文所提出的混合數字系統硬體化系統架構旨在解決以上問題。硬體化系統架構有以下三個優點: i) 低花費的FPGA邏輯元件; ii) 高運算效能; iii) 高精度的算術運算。經由實驗結果得知,透過混合數字系統能有效提升TS-CMAC的算術運算速度,同時在設計算術硬體上減少佔用面積並保有高數字精確度,達到TS-CMAC在控制上之準確性。
    In this paper, we developed a hardware intelligent controller, such as TS-CMAC, implemented on a field programmable gate array (FPGA) platform. We also discuss the impact of arithmetic representation on computing performance of controller. In addition, we implemented a 32-bit hybrid number system processor for TS-CMAC arithmetic operations. However, arithmetic representations for intelligent controller is dependent on computing performance. The tradeoff between precision and representation along with FPGA logic element costs requirements are considered. Therefore, our hardware system architecture seek to fill the gap between why. We proposed hybrid number system for our controller arithmetic representation. The hardware system architecture has advantages: i) low costs of hardware logic element; ii) high computing performance; iii) high accuracy of arithmetic operation. According to experimental results, TS-CMAC arithmetic operation speed can be increased effectively by hybrid number system which can not only reduce area occupied of hardware but also maintain high precision in arithmetic hardware design, and thus enhance TS-CMAC accuracy in intelligent control .
    顯示於類別:[電機工程學系暨研究所] 學位論文

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