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    Title: 低輸入電壓之數位式控制低壓降線性穩壓器
    Other Titles: Low input voltage 90nm digitally controlled LDO
    Authors: 謝少鈞;Xie, Shao-Jyun
    Contributors: 淡江大學電機工程學系碩士班
    楊維斌;Yang, Wei-Bin
    Keywords: 數位式穩壓器;低功耗;低於0.5V;Digital LDO;low power;Sub -0.5V
    Date: 2014
    Issue Date: 2015-05-04 10:02:15 (UTC+8)
    Abstract: 基於現今電子器材要求降低功率消耗的概念下,本論文提出了以降低輸入電壓為首要工作之低壓降線性穩壓器。在90nm製程下,輸入電壓為1V為基本,如何降低到0.5V以下系統人然能夠正常運作便是研究中的一個重要議題。低壓降線性穩壓器運用於提供穩定電壓,穩壓器是否能精確地輸出電壓為極重要的,因此,要判斷出穩壓器的可靠度及準確度,線性調節率與負載調節率變為重要的參數。
    本論文提出的電路可分為三部分,第一部分為粗調控制,利用漸進式移位暫存控制器的二分法概念產生出數位訊號控制功率電晶體以達到快速地輸出電壓,第二部分則為細調控制,以移位暫存器來細微調整輸出電壓的大小,使輸出電壓可以及靠近目標電壓,以求精準度,第三部分為比較器,此電路直接影響著整體電路事整體電路的精確度。由於功率電晶體會隨著製程及溫度偏異而改變,功率電晶體的大小便為重要,在此利用11 bit的移位暫存控制器來驅使足夠大的電晶體以求達到理想的輸出電壓,由於此時輸出電壓還未達到目標電壓,未達到相當精確,因此加入80級的移位暫存器來控制尺寸極小的功率電晶體,此微調範圍可包含於TT、FF、SS三種製程以及0°C、25°C及75°C三種溫度,使得規格都有符合預期之規格。
    上述的電路設計加以模擬驗證後可得到一輸入電壓低於0.5V之數位式超低壓低壓降線性穩壓器,輸入電壓為0.5V,輸出電壓為0.3V。最大負載電流為5mA,與精準度有關的負載調節率可達到0.516mV/mA,線性調節率達到6.88 mV/V,而靜態電流卻僅為26uA。
    In this paper, the concept based on low power consumption, and reducing the input voltage is become the top priority. In 90nm process, the input voltage of 1V to basic, how to reduce to less 0.5V is an important topic in the study of normal operation. Low dropout regulator should be applied to provide a stable voltage, and the accuracy of output voltage is extremely important. So the line regulation and the load regulation will be the accuracy of the reference indicators.
    Therefore, the overall circuit can be divided into three parts. The first part is using SAR_Control digital signal to turn on the power transistor for achieving the output voltage. The second part is using shift register to fine tuning output voltage in order to accuracy. The third part is comparator. The size of power transistor will be important because the limit of the load current. Using 11 bit SAR_Control to drive transistor large enough for achieving the desired output voltage. The output voltage only close to the desired voltage, and it does not meet the extremely accurate. So adding 80 bit shift register to control the small size power transistor. The fine tuning range can be included in the TT, FF, SS, three kind of process, and can be meet the expected specifications.
    Though the above mentioned circuit design and simulation can be obtained a low input voltage Digitally Controlled LDO. The input voltage is 0.5V, and output voltage is 0.3V. When the heavy load current is 5mA, the line regulation is 0.516mV / mA, the load regulation is 6.88mV/V and the quiescent is only 26uA.
    Appears in Collections:[電機工程學系暨研究所] 學位論文

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