English  |  正體中文  |  简体中文  |  Items with full text/Total items : 51931/87076 (60%)
Visitors : 8494506      Online Users : 97
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/102698

    Title: 具有軌對軌輸出入信號之低功耗高增益運算放大器之設計
    Other Titles: Design of low-power high-gain operational amplifier with rail-to-rail input and output ranges
    Authors: 許媛雯;Hsu, Yuan-Wen
    Contributors: 淡江大學電機工程學系碩士在職專班
    郭建宏;Kuo, Chien-Hung
    Keywords: 運算放大器;軌對軌;固定轉導;增益提高組態;amplifier;Rail-to-Rail;constant-gm;gain-boosting
    Date: 2014
    Issue Date: 2015-05-04 10:02:10 (UTC+8)
    Abstract: 隨著時代的改變,運算放大器(Operational Amplifier)有各類型不同的應用與製程選擇,超大型積體電路(VLSI)與互補式金屬氧化性半導體(CMOS)在製程上不斷的改進,運算放大器因此在設計有較多選擇。在現代新的應用上傾向高增益、低功耗、全擺幅輸出入、高穩定度、高推力、低成本等需求,因此本文提供之運算放大器設計目標為儘量符合以上需求。
    整體電路包含三大部分,第一部分為差動輸入級,含軌對軌輸入端及固定轉導控制器,第二部分為疊接增益級,含疊接組態、浮動電流源及增益提高組態之組合,第三部分為單端輸出級,為一AB類推挽放大器。最後目標為期望規格到達增益(Gain)為120dB以上,相位安全邊限(Phase Margin)為60°~63°左右,單增益頻寬(Unity-gain frequency)為1.5MHz,消耗功率(power consumption)為0.37mW左右,輸出入均可達最大擺幅,並可推動最高負載電容50pF或最低負載電阻10kΩ等。
    本設計採用國家晶片系統設計中心(CIC) 0.35μm 2P4M CMOS製程,根據驗證結果,本設計的實際規格可以到達增益為123dB,相位安全邊限為61.4°,單增益頻寬為1.52MHz,消耗功率為0.37mW,輸出入擺幅可由最低0V到最高3.3V,並可穩定推動負載電容50pF或負載電阻10kΩ。
    This thesis presents an operational amplifier which function could meet the new requirement of nowadays. Following the improvement of VLSI (Very Large Scale Integrated Circuits) design and CMOS (Complementary Metal Oxide Semiconductor) process, the design of OPA (Operational Amplifier) has many choices for different applications and purposes. The new tendency of OPA applications would be high gain, low power consumption, rail-to-rail input/output range, better stability, better driving capability and low cost, etc., which would be the goal of this proposed OPA to be designed.
    The architecture of this proposed OPA includes 3 major stages: the first stage is the differential inputs stage combined with constant-gm controller; the second stage is the folded-cascode amplifier stage constructed of cascode, floating current source and gain boosting amplifiers; the third stage is the single-ended output stage consisted of a class AB push-pull amplifier. The goal of this OPA is to achieve that gain equals over 120dB, phase margin equals around 60°~63°, unity-gain frequency equals 1.5MHz, power consumption equals 0.37mW, the input/output range reaches the maximum, and the driving load is up to 50pF capacitor or lowest to 10kΩ resistor, etc.
    The fabrication of this proposed OPA is implemented by the 0.35μm 2P4M CMOS process of CIC (Chip Implementation Center). The final result of this OPA is that gain equals 123dB, phase margin 61.4°, unity-gain frequency 1.52MHz, power consumption equals 0.37mW, the input/output range reaches from 0V to 3.3V, and the driving load is stable up to 50pF capacitor or lowest to 10kΩ resistor.
    Appears in Collections:[電機工程學系暨研究所] 學位論文

    Files in This Item:

    File SizeFormat

    All items in 機構典藏 are protected by copyright, with all rights reserved.

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback