此篇論文提出一Coarse-Fine TDC架構，此架構將Coarse TDC送進TA(Time Amplifier) 時間放大器裡放大，放大後的取樣誤差再至 Fine TDC架構中再取樣一次，藉此增加整個TDC的解析度。此Coarse-Fine TDC架構可應用於全數位式鎖向迴路(ALL digital PLL)的電路架構中，用以降低All digital PLL輸出訊號之in-band相位雜訊，達到產生高速與低抖動(Jitter)時脈訊號之目的。 With the improvement of technology, the requirement of electronic products is getting faster and smaller than before. Operating speed of transistor is getting faster and faster, with this problem the operating voltage of the transistor is getting low. Therefore, it not easy in designing circuit with high speed, high gain and low operating voltage.
Recently years, Time-to-Digital converter used for detecting time interval of specific event are widely applied in many fields such like all digital Phase-Lock-Loop, chip’s jitter, single molecule fluorescence spectroscopy, fluorescence imaging and laser scanning microscopy. In high speed situation, there are some very important issues about clock measurement. The data transmission and reception and the noise interference problems.
This paper proposes a Coarse-Fine TDC. This architecture put the signal which produced by Coarse TDC into TA. Coarse TDC can find out the deviation then put it into TA. Because of the TA, we can Enlarge the deviation then use Fine TDC processing again. By this way, we can promote the resolution effectively
