English  |  正體中文  |  简体中文  |  Items with full text/Total items : 62830/95882 (66%)
Visitors : 4035620      Online Users : 884
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/102656


    Title: 可變傳輸速率之超低功耗頻率鍵移接收器電路
    Other Titles: An ultra-low power multi-rate FSK receiver in 0.18 μm CMOS process
    Authors: 王俊鴻;Wang, Chun-Hung
    Contributors: 淡江大學電機工程學系碩士班
    施鴻源;Shih, Horng-Yuan
    Keywords: 超低功耗;接收器;頻率鍵移;Ultra-Low Power;Weak Inversion;Receiver;FSK
    Date: 2014
    Issue Date: 2015-05-04 10:01:13 (UTC+8)
    Abstract: 隨著科技的蓬勃發展,生醫電子也逐漸的和許多產品結合,將穿戴式行動通訊產品加入生醫晶片用以偵測各種生理訊號,用以協助使用者得知目前生理狀況為目的的設計已成為了趨勢。由於此類產品須長時間於戶外使用,而電源來源主要來自電池、體熱發電或是無線電能量收集電路,因此在其傳輸介面電路設計上超低功率消耗成了最重要的考量。

    此外,接收器在使用上須長時間維持開啟狀態,占了大半部分的功耗,因此實現一超低功耗接收器便可大幅降低耗電量,延長使用的時間。

    本論文提出一超低功耗與可變傳輸速率之頻率鍵移接收器,在傳輸速率上,突破了以往於超低功耗的設計下最快10 Mb/s的限制。另外,依傳輸資料總類的不同,其所需的最佳傳輸速率也不盡相同,而本接收器亦可依據使用者的需求調整其最高接收速率,以達到最佳化的目的。

    在傳輸訊號選擇方面,使用了FSK調變解調,其相較於其它調變具有較的低複雜度與較高的抗干擾能力,因此特別適用於超低功耗傳輸系統。延遲電路設計方面,則使用了寬頻電流式放大器電路,實現了電流式的相位位移電路,達到800 μA的電流消耗下,此相位鍵移接收器具有20 Mb/s之資料傳輸速度,以達到超低功率消耗與縮短傳輸所需時間的目的。
    An ultra-low power (ULP) frequency shift keying (FSK) receiver had be applied for wearable or implantable physiology sensors in recent years. Comparing to the other signal modulation, FSK provides better immunity against interference. Therefore, the ULP FSK receiver is suitable to provide stable link quality and extend life time of sensors. In this paper, we propose an ultra-low power, high data rate and variable data rate FSK receiver. The ULP FSK receiver was combined by a ULP Front-end and a ULP demodulator. Otherwise, we use current-mode phase shifter to improve bandwidth of the demodulator. High energy efficiency can be achieved by reducing the energy consumption per received bit of FSK receiver. Owing to variable data rate of the FSK demodulator, the power consumption of the FSK receiver can be trade-off for optimization under different operating conditions.

    The ULP FSK receiver was implemented in 0.18 μm CMOS process. The simulated maximum data rate is 20 Mb/s under power consumption of 1.44 mW. Therefore, the minimum energy consumption of 72 pJ per received bit can be achieved under maximum data rate of 20 Mb/s.
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Thesis

    Files in This Item:

    File SizeFormat
    index.html0KbHTML184View/Open

    All items in 機構典藏 are protected by copyright, with all rights reserved.


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback