English  |  正體中文  |  简体中文  |  Items with full text/Total items : 52047/87178 (60%)
Visitors : 8712539      Online Users : 189
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/101672

    Title: 軟硬體共同設計於取放作業之路徑規劃
    Other Titles: Hardware/software co-design of pick and place operations for path planning
    Authors: 翁仲緯;Weng, Chung-Wei
    Contributors: 淡江大學電機工程學系碩士班
    Keywords: 軟硬體共同設計;蟻群演算法;抓取與放置;路徑規劃;Hardware/software co-design;FPGA;Ant Colony Algorithm;Pick and place;Path Planning
    Date: 2014
    Issue Date: 2015-05-01 16:13:52 (UTC+8)
    Abstract: 本論文提出以改良式蟻群演算法為基礎的蟻群硬體加速器,應用於取放作業任務物件取放順序的路徑規劃,並使用ALTERA DE2i-150 FPGA開發平台實現軟硬體共同設計的系統架構。
    本論文使用INTEL ATOM處理器與ALTERA FPGA處理器並行的DE2i-150開發平台,透過軟硬體共同設計的方法,將蟻群演算法運算功能作軟體運算以及硬體運算的區分,軟體主要用於處理浮點數的運算,硬體主要用於處理重覆程序的運算,並藉由調整蟻群最佳化演算法的路徑起訖表與費洛蒙更新等方法而提出的改良式蟻群演算法,於FPGA處理器中設計以此為基礎的蟻群硬體加速器,試圖以系統分工的觀念提升蟻群演算法的系統效能以及穩定度。
    In this thesis, an improved ant colony algorithm-based ant colony hardware accelerator is proposed. It is applied to pick and place task for planning the path of picking objects'' sequences based on ALTERA DE2i-150 development kit platform to implement the architecture of hardware/software co-design system.
    In this thesis, ALTERA DE2i-150 development kit platform has two main processor, INTEL ATOM processor and ALTERA FPGA processor, executing simultaneously. According to the method of hardware/software co-design, the computing functions are divided into software and hardware. Software is used to process float-point computation, and hardware is used to process repeat procedure computation. Due to the method of changing terminal table and pheromone updating, this thesis proposes an improved ant colony algorithm and designs an improved ant colony algorithm-based hardware accelerator into the FPGA processor. This thesis attempts to use the concept of system division to enhance the performance and stability of the system.
    According to the results, the ant colony hardware accelerator can enhance the performance and stability of the system indeed. It not only decreases the processing time of the path planning system but also keeps the search results stability.
    Appears in Collections:[電機工程學系暨研究所] 學位論文

    Files in This Item:

    File SizeFormat

    All items in 機構典藏 are protected by copyright, with all rights reserved.

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback