本論文提出以改良式蟻群演算法為基礎的蟻群硬體加速器，應用於取放作業任務物件取放順序的路徑規劃，並使用ALTERA DE2i-150 FPGA開發平台實現軟硬體共同設計的系統架構。 本論文使用INTEL ATOM處理器與ALTERA FPGA處理器並行的DE2i-150開發平台，透過軟硬體共同設計的方法，將蟻群演算法運算功能作軟體運算以及硬體運算的區分，軟體主要用於處理浮點數的運算，硬體主要用於處理重覆程序的運算，並藉由調整蟻群最佳化演算法的路徑起訖表與費洛蒙更新等方法而提出的改良式蟻群演算法，於FPGA處理器中設計以此為基礎的蟻群硬體加速器，試圖以系統分工的觀念提升蟻群演算法的系統效能以及穩定度。 由實驗結果可知，蟻群硬體加速器確實提升系統的效能以及穩定度，減少蟻群演算法用於路徑規劃的運算時間以及提供穩定的路徑搜尋結果。 In this thesis, an improved ant colony algorithm-based ant colony hardware accelerator is proposed. It is applied to pick and place task for planning the path of picking objects'' sequences based on ALTERA DE2i-150 development kit platform to implement the architecture of hardware/software co-design system. In this thesis, ALTERA DE2i-150 development kit platform has two main processor, INTEL ATOM processor and ALTERA FPGA processor, executing simultaneously. According to the method of hardware/software co-design, the computing functions are divided into software and hardware. Software is used to process float-point computation, and hardware is used to process repeat procedure computation. Due to the method of changing terminal table and pheromone updating, this thesis proposes an improved ant colony algorithm and designs an improved ant colony algorithm-based hardware accelerator into the FPGA processor. This thesis attempts to use the concept of system division to enhance the performance and stability of the system. According to the results, the ant colony hardware accelerator can enhance the performance and stability of the system indeed. It not only decreases the processing time of the path planning system but also keeps the search results stability.