A Low Phase Noise All-Digital Programmable DLL-Based Clock Generator

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Title:	A Low Phase Noise All-Digital Programmable DLL-Based Clock Generator
Authors:	Lo, Yu-Lung;Liu, Han-Ying;Chou, Pei-Yuan;Yang, Wei-Bin
Contributors:	淡江大學電機工程學系
Date:	2014-04-26
Issue Date:	2015-04-13 19:00:25 (UTC+8)
Abstract:	This paper proposes a low phase noise all-digital programmable DLL-based clock generator. The proposed clock generator is fabricated in a 0.18 μm standard CMOS process with a 1.8 V supply voltage. The proposed digital programmable DLL-based clock generator is easy migration over different processes and low power dissipation. The measurement results show that the input and output frequency ranges can operate 100 MHz ~ 600 MHz and 100 MHz ~ 1.2 GHz, respectively. At 800 MHz, the phase noise is -112.36 dBc @ 1MHz offset frequency. The total power consumption of the clock generator is 23.87 mW, and the active die area of the clock generator is 0.14 mm2.
Relation:	pp.1572-1575
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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