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    題名: A Low Phase Noise All-Digital Programmable DLL-Based Clock Generator
    作者: Lo, Yu-Lung;Liu, Han-Ying;Chou, Pei-Yuan;Yang, Wei-Bin
    貢獻者: 淡江大學電機工程學系
    日期: 2014-04-26
    上傳時間: 2015-04-13 19:00:25 (UTC+8)
    摘要: This paper proposes a low phase noise all-digital programmable DLL-based clock generator. The proposed clock generator is fabricated in a 0.18 μm standard CMOS process with a 1.8 V supply voltage. The proposed digital programmable DLL-based clock generator is easy migration over different processes and low power dissipation. The measurement results show that the input and output frequency ranges can operate 100 MHz ~ 600 MHz and 100 MHz ~ 1.2 GHz, respectively. At 800 MHz, the phase noise is -112.36 dBc @ 1MHz offset frequency. The total power consumption of the clock generator is 23.87 mW, and the active die area of the clock generator is 0.14 mm2.
    關聯: pp.1572-1575
    顯示於類別:[電機工程學系暨研究所] 會議論文

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